1. Field of Invention
The present invention relates to a semiconductor packaging technology, and more particularly to a multi-chip package (MCP) with a spacer that is inserted between chips and a manufacturing method thereof.
2. Description of Related Art
It has been long desired to provide low-cost semiconductor chip packages that are lighter, smaller, with higher speed, multi-function, and with improved reliability. In order to satisfy this goal, a multi-chip packaging technique has been developed. The multi-chip package comprises same or different types of plural chips being assembled into a single unit package. Compared to using a plurality of packages, each including a single chip, the multi-chip package has advantages in miniaturization, light-weight, and high surface-mount density.
These multi-chip packages are classified into two types, i.e., a vertical-stacking type and a parallel-aligning type. The former reduces mounting area, while the latter simplifies the manufacturing process and reduces package thickness. In order to achieve miniaturization and light-weight, the vertical-stacking type has been more commonly used in multi-chip packages. The conventional vertical-stacking type of the multi-chip package is described below.
FIG. 1 is a cross-sectional view of a conventional multi-chip package 110. The multi-chip package 110 comprises a first chip 111 mounted on a substrate 121 and a second chip 113 mounted on the first chip 111. The active surfaces 111a, 113a of the first and second chips 111, 113 are upward. The back surface 111b of the first chip 111 is mounted on the substrate 121 and the back surface 113b of the second chip 113 is mounted on the active surface of the first chip 111. Chip pads 112 of the first chip 111 and chip pads 114 of the second chip 113 are electrically connected to corresponding bonding pads 123 by bonding wires 141, 143. The entire assembly including the first chip 111, the second chip 113 and other electrical connection elements is encapsulated with an encapsulant such as an epoxy molding resin to form a package body 151. Solder balls 161 are attached to corresponding land patterns of the bottom surface of the substrate 121 and serve as external connection terminals.
The conventional multi-chip package comprises a plurality of semiconductor chips, thereby achieving better electrical performance and higher integrity at lower cost. Further, the area-arrayed external connection terminals of the multi-chip package satisfy the trend of the ever-increasing numbers of input/output pins.
However, this conventional vertical-stacking multi-chip package structure limits the type and the size of chips.
Since the chip requires a bonding area for the wire-bonding, the size of the upper chip should be reduced by being stacked upwards. If the lower chip is smaller than the upper chip, the chip pads of the lower chip are shielded by the upper chip, thereby preventing the wire-bonding between the chip pads of the lower chip and the bonding pads of the substrate.
Moreover, since the conventional multi-chip package needs to be individually assembled, it cannot be mass-produced.